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19-1399; Rev 1; 6/03
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
General Description
The MAX1108/MAX1109 low-power, 8-bit, dual-channel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H) voltage reference, clock, and serial interface. The MAX1108 is specified from +2.7V to +3.6V and consumes only 105A. The MAX1109 is specified from +4.5V to +5.5V and consumes only 130A. The analog inputs are software configurable, allowing unipolar/bipolar and single-ended/differential operation; battery monitoring capability is also included. The full-scale analog input range is determined by the internal reference of +2.048V (MAX1108) or +4.096V (MAX1109), or by an externally applied reference ranging from 1V to VDD. The MAX1108/MAX1109 also feature a software power-down mode that reduces power consumption to 0.5A when the device is not in use. The 4-wire serial interface directly connects to SPITM, QSPITM, and MICROWIRETM devices without external logic. Conversions up to 50ksps are performed using either the internal clock or an external serial-interface clock. The MAX1108 and MAX1109 are available in a 10-pin MAX package with a footprint that is just 20% of an 8-pin plastic DIP.
Features
o Single Supply: +2.7V to +3.6V (MAX1108) +4.5V to +5.5V (MAX1109) o Low Power: 105A at +3V and 50ksps 0.5A in Power-Down Mode o Software-Configurable Unipolar or Bipolar Inputs o Input Voltage Range: 0 to VDD o Internal Track/Hold o Internal Reference: +2.048V (MAX1108) +4.096V (MAX1109) o Reference Input Range: 1V to VDD o SPI/QSPI/MICROWIRE-Compatible Serial Interface o VDD Monitoring Mode o Small 10-Pin MAX Package
MAX1108/MAX1109
Ordering Information
PART MAX1108CUB MAX1108EUB MAX1109CUB MAX1109EUB TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PIN-PACKAGE 10 MAX 10 MAX 10 MAX 10 MAX
Applications
Portable Data Logging Hand-Held Measurement Devices Medical Instruments System Diagnostics Solar-Powered Remote Systems 4-20mA-Powered Remote Systems Receive-Signal Strength Indicators
Functional Diagram
VDD CS SCLK INPUT SHIFT REGISTER OUTPUT SHIFT REGISTER
Pin Configuration
DIN
DOUT
TOP VIEW
VDD 1 CH0 CH1 GND REF 2 3 4 5 10 SCLK 9 DOUT DIN CS COM
REF
MAX1108 MAX1109
CONTROL LOGIC CH0 CH1 COM ANALOG INPUT MUX INTERNAL REFERENCE T/H
INTERNAL OSCILLATOR
SAR
MAX1108 MAX1109
8 7 6
CHARGE REDISTRIBUTION DAC
MAX
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
GND
________________________________________________________________ Maxim Integrated Products
1
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Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V CH0, CH1, COM, REF, DOUT to GND .......-0.3V to (VDD + 0.3V) DIN, SCLK, CS to GND ............................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 10-pin MAX (derate 5.6mW/C above +70C) ............444mW Operating Temperature Ranges MAX110_CUB ......................................................0C to +70C MAX110_EUB ...................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX1108
(VDD = +2.7V to +3.6V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock mode (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1F capacitor at REF, external +2.048V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY Resolution Relative Accuracy (Note 1) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Total Unadjusted Error Channel-to-Channel Offset Matching VDD / 2 Sampling Accuracy DYNAMIC PERFORMANCE (10kHz sine-wave input, 2.048Vp-p, 50ksps, 500kHz external clock) Signal-to-Noise Plus Distortion Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth ANALOG INPUTS Unipolar input, VCOM = 0 Input Voltage Range (Note 4) VCH_ Bipolar input, VCOM or VCH1 = VREF / 2, referenced to COM or CH1 On/off-leakage current, VCOM or VCH = 0 or VDD CIN 0.01 18 0 VREF VREF / 2 1 V SINAD THD SFDR BW-3dB -3dB rolloff 49 -70 68 1.5 0.8 dB dB dB MHz MHz TUE TA = +25C TA = TMIN to TMAX 0.5 0.1 50 0.8 1 INL DNL VDD = 2.7V to 3.6V VDD = 5.5V (Note 2) No missing codes over temperature VDD = 2.7V to 3.6V VDD = 5.5V (Note 2) 0.2 0.5 1 8 0.15 0.2 1 1 0.5 bits LSB LSB LSB LSB ppm/C LSB LSB mV SYMBOL CONDITIONS MIN TYP MAX UNITS
Multiplexer Leakage Current Input Capacitance
A pF
2
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Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS--MAX1108 (continued)
(VDD = +2.7V to +3.6V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock mode (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1F capacitor at REF, external +2.048V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER TRACK/HOLD Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency Range INTERNAL REFERENCE Output Voltage REF Short-Circuit Current REF Tempco Load Regulation Capacitive Bypass at REF EXTERNAL REFERENCE Input Voltage Range Input Current POWER REQUIREMENTS Supply Voltage VDD VDD = 2.7V to 3.6V, CL = 10pF Supply Current (Notes 2, 8) IDD VDD = 5.5V, CL = 10pF Internal reference External reference Internal reference External reference 2.7 3 105 70 130 95 0.5 0.4 2.5 4 2 3 0.8 0.2 1 1 15 mV V V V V A A pF 5.5 250 A A V +2.048V at REF, full scale, 500kHz external clock 1.0 1 VDD + 0.05 20 V A 0 to 0.5mA (Note 7) 1 VREF IREFSC (Note 6) 1.968 2.048 150 50 2.5 2.128 V A ppm/C mV F 50 For data transfer only tCONV tACQ Internal clock External clock, 500kHz, 10 sclks/conv External clock, 2MHz 20 1 10 <50 400 500 2 35 s s ns ps kHz kHz MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1108/MAX1109
Power down, VDD = 2.7V to 3.6V (Note 9) Power-Supply Rejection (Note 10) PSR Full-scale input, VDD = 2.7V to 3.6V VDD 3.6V VDD > 3.6V DIGITAL INPUTS (DIN, SCLK, and CS) Threshold Voltage High Threshold Voltage Low Input Hysteresis Input Current High Input Current Low Input Capacitance VIH VIL VHYST IIH IIL CIN
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3
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
ELECTRICAL CHARACTERISTICS--MAX1108 (continued)
(VDD = +2.7V to +3.6V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock mode (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1F capacitor at REF, external +2.048V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance Acquisition Time DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low Wake-Up Time Wake-Up Time VOH VOL IL COUT tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tWAKE External reference Internal reference (Note 11) Figure 1, CLOAD = 100pF Figure 1, CLOAD = 100pF Figure 2, CLOAD = 100pF 100 0 200 200 20 12 ISOURCE = 0.5mA ISINK = 5mA ISINK = 16mA CS = VDD CS = VDD 1.0 100 0 20 200 240 240 0.8 0.01 15 10 VDD - 0.5 0.4 V V V A pF s ns ns ns ns ns ns ns ns ns s ms SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figures 8, 9, and 10)
ELECTRICAL CHARACTERISTICS--MAX1109
(VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1F capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY Resolution Relative Accuracy (Note 1) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Total Unadjusted Error Channel-to-Channel Offset Matching VDD / 2 Sampling Accuracy TUE TA = +25C TA = TMIN to TMAX 0.5 0.1 50 0.8 1 INL DNL VDD = 4.5V to 5.5V No missing codes over temperature VDD = 4.5V to 5.5V 0.2 8 0.15 0.5 1 1 1 bits LSB LSB LSB LSB ppm/C LSB LSB mV SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS--MAX1109 (continued)
(VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1F capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Signal-to-Noise Plus Distortion Total Harmonic Distortion (up to the 5th harmonic) Spurious Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth ANALOG INPUTS Unipolar input, VCOM = 0 Input Voltage Range (Note 4) VCH_ Bipolar input, VCOM or VCH1 = VREF / 2, referenced to COM or CH1 On/off-leakage current, VCH = 0 or VDD CIN Internal clock External clock, 500kHz, 10 sclks/conv External clock, 2MHz 20 1 10 <50 400 50 For data transfer only VREF IREFSC 0 to 0.5mA (Note 7) 1 1.0 +4.096V at REF, full scale, 500kHz external clock 1 VDD + 0.05 20 3.936 4.096 5 50 2.5 500 2 4.256 0.01 18 35 0 VREF VREF / 2 1 V SYMBOL SINAD THD SFDR BW-3dB -3dB rolloff CONDITIONS MIN TYP 49 -70 68 1.5 0.8 MAX UNITS dB dB dB MHz MHz DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)
MAX1108/MAX1109
Multiplexer Leakage Current Input Capacitance TRACK/HOLD Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency Range INTERNAL REFERENCE Output Voltage REF Short-Circuit Current REF Tempco Load Regulation Capacitive Bypass at REF EXTERNAL REFERENCE Input Voltage Range Input Current tCONV tACQ
A pF
s s ns ps kHz kHz MHz V mA ppm/C mV F V A
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5
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
ELECTRICAL CHARACTERISTICS--MAX1109 (continued)
(VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1F capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER POWER REQUIREMENTS Supply Voltage VDD VDD = 4.5V to 5.5V, CL = 10pF, full-scale input Internal reference External reference 4.5 5 130 95 0.5 0.4 2.5 4 mV 5.5 250 A A V SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current (Notes 2, 8)
IDD
Power down, VDD = 4.5V to 5.5V (Note 9) Power-Supply Rejection (Note 10) PSR External reference = +4.096V, full-scale input, VDD = 4.5V to 5.5V
DIGITAL INPUTS (DIN, SCLK, and CS) Threshold Voltage High Threshold Voltage Low Input Hysteresis Input Current High Input Current Low Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance Acquisition Time DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable VOH VOL IL COUT tACQ tDS tDH tDO tDV tTR Figure 1, CLOAD = 100pF Figure 1, CLOAD = 100pF Figure 2, CLOAD = 100pF ISOURCE = 0.5mA ISINK = 5mA ISINK = 16mA CS = VDD CS = VDD 1.0 100 0 20 200 240 240 0.8 0.01 15 10 VDD - 0.5 0.4 V V A pF s ns ns ns ns ns VIH VIL VHYST IIH IIL CIN 15 0.8 0.2 1 1 3 V V V A A pF
TIMING CHARACTERISTICS (Figures 8, 9, and 10)
6
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Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS--MAX1109 (continued)
(VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1F capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low Wake-Up Time SYMBOL tCSS tCSH tCH tCL tWAKE External reference Internal reference (Note 11) CONDITIONS MIN 100 0 200 200 20 12 TYP MAX UNITS ns ns ns ns s ms
MAX1108/MAX1109
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 2: See Typical Operating Characteristics. Note 3: VREF = +2.048V (MAX1108), VREF = +4.096V (MAX1109), offset nulled. Note 4: Common-mode range (CH0, CH1, COM) GND to VDD. Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle (Figures 6 and 8). Note 6: REF supplies typically 2.5mA under normal operating conditions. Note 7: External load should not change during the conversion for specified accuracy. Note 8: Power consumption with CMOS levels. Note 9: Power-down test performed using the following sequence 1) SHDN 5bit = 0 in the configuration register; 2) Wait for 10 SCLK cycles to complete current conversion; 3) Measure shutdown current with CS, SCLK, DIN = VDD or GND. Note 10: Measured as VFS(2.7V) - VFS(3.6V) for MAX1108, and measured as VFS(4.5V) - VFS(5.5V) for MAX1109. Note 11: 1F at REF, internal reference settling to 0.5LSB.
Typical Operating Characteristics
(VDD = +3.0V (MAX1108), VDD = +5.0V (MAX1109); external conversion mode; fSCLK = 500kHz; 50ksps; external reference; 1F at REF; TA = +25C; unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1108/09-02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1108/09-01
SUPPLY CURRENT vs. TEMPERATURE
200 180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 20 0 DOUT = 10101010 CLOAD = 10pF INTERNAL REFERENCE -40 -20 0 20 40 60 80 100 VDD = 3V VDD = 5V 0.50 0.45 SHUTDOWN CURRENT (A) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 2.5
180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 20 0 0 1 2 3
CLOAD = 47pF
CLOAD = 10pF
DOUT = 10101010 MAX1108 (2.7V TO 5.5V) MAX1109 (4.5V TO 5.5V) INTERNAL REFERENCE 4 5 6
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
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7
MAX1108/09-03
200
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX1108), VDD = +5.0V (MAX1109); external conversion mode; fSCLK = 500kHz; 50ksps; external reference; 1F at REF; TA = +25C; unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX1108/09-04 MAX1108/09-05
OFFSET ERROR vs. SUPPLY VOLTAGE
0.5 0.4 0.3 OFFSET ERROR (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 0.5 0.4 0.3 OFFSET ERROR (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -40
OFFSET ERROR vs. REFERENCE VOLTAGE
0.15 OFFSET ERROR (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
MAX1108/09-06
0.20
-20
0
20
40
60
80
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
TEMPERATURE (C)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1108/09-07
GAIN ERROR vs. TEMPERATURE
0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1108/09-08
GAIN ERROR vs. REFERENCE VOLTAGE
0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1108/09-09
0.5 0.4 0.3 GAIN ERROR (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.5 3.0 3.5 4.0 4.5 5.0
1.0
1.0
5.5
-40
-20
0
20
40
60
80
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX1108/09-10
DIFFERENTIAL NONLINEARITY vs. CODE
MAX1108/09-11
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX1108/09-12
0.3 0.2 0.1
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4
0.5
INL (LSB)
0 -0.1 -0.2 -0.3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-0.5 0 50 100 150 200 250 300 DIGITAL CODE
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
8
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Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX1108), VDD = +5.0V (MAX1109); external conversion mode; fSCLK = 500kHz; 50ksps; external reference; 1F at REF; TA = +25C; unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
MAX1108/09-13
MAX1108/MAX1109
FFT PLOT
MAX1108/09-14
CONVERSION TIME vs. SUPPLY VOLTAGE
INTERNAL CONVERSION MODE 20.5 CONVERSION TIME(s) 20.0 19.5 19.0 18.5 18.0
MAX1108/09-15
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 50 100 150 200 250
20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100
fCH_ = 9997Hz, 2Vp-p fSAMPLE = 53.25kHz
21.0
300
0
5
10
15
20
25
30
0
1
2
3
4
5
6
DIGITAL CODE
FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
CONVERSION TIME vs. TEMPERATURE
MAX1108/09-16
NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE
MAX1108/09-17
CHANNEL-TO-CHANNEL CROSSTALK vs. FREQUENCY
-10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 -80 -90 VCH_OFF = VREFp-p
MAX1108/09-18
25 24 23 CONVERSION TIME (s) 22 21 20 19 18 17 16 15 -40 -20 0 20 40 60 80 VDD = 5V VDD = 3V INTERNAL CONVERSION MODE
1.0010 1.0005 REFERENCE VOLTAGE (V) 1.0000 0.9995 0.9990 0.9985 0.9980
0
-100 -40 -20 0 20 40 60 80 100 0 5 10 15 20 25 TEMPERATURE (C) FREQUENCY (kHz)
100
TEMPERATURE (C)
Pin Description
PIN 1 2, 3 4 5 6 7 8 9 10 NAME VDD CH0, CH1 GND REF COM CS DIN DOUT SCLK Positive Supply Voltage Sampling Analog Inputs Ground Reference voltage for analog-to-digital conversion (internal or external reference). Reference input for external reference. Bypass internal reference with 1F capacitor to GND. Common reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to 0.5LSB during conversion. Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial Data Input. Data is clocked in at the rising edge of SCLK. Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is high. Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. _______________________________________________________________________________________ 9 FUNCTION
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
VDD VDD 3k DOUT DOUT
DOUT
DOUT
3k
3k DGND a) High-Z to VOH and VOL to VOH
CLOAD
CLOAD DGND b) High-Z to VOL and VOH to VOL
3k DGND a) VOH to High-Z
CLOAD
CLOAD DGND b) VOL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________Detailed Description
The MAX1108/MAX1109 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to an 8-bit digital output. A flexible serial interface provides easy interface to microprocessors (Ps). No external hold capacitors are required. All of the MAX1108/MAX1109 operating modes are software-configurable: internal or external reference, internal or external conversion clock, single-ended unipolar or pseudo-differential unipolar/bipolar conversion, and power down (Table 1).
VDD CH0 ANALOG INPUTS CH1 VDD 0.1F GND COM 1F VDD
CPU MAX1108 MAX1109
REF 1F CS SCLK DIN DOUT I/O SCK (SK) MOSI (SO) MISO (SI) VSS
Analog Inputs
Track/Hold The input architecture of the ADCs is illustrated in the equivalent-input circuit of Figure 4 and is composed of the T/H, the input multiplexer, the input comparator, the switched capacitor DAC, the reference, and the autozero rail. The analog-inputs configuration is determined by the control-byte through the serial interface as shown in Table 2 (see Modes of Operation section and Table 1). The eight modes of operation include single-ended, pseudo-differential, unipolar/bipolar, and a VDD monitoring mode. During acquisition and conversion, only one of the switches in Figure 4 is closed at any time. The T/H enters its tracking mode on the falling clock edge after bit 4 (SEL0) of the control byte has been shifted in. It enters its hold mode on the falling edge after the bit 2 (I/EREF) of the control byte has been shifted in. For example, If CH0 and COM are chosen (SEL2 = SEL1 = SEL0 = 1) for conversion, CH0 is defined as the sampled input (SI), and COM is defined as the reference input (RI). During acquisition mode, the CH0 switch and the T/H switch are closed, charging the
10
Figure 3. Typical Operating Circuit
GND CAPACITIVE DAC REF CH1 CH0 COM VDD / 2 GND AUTOZERO RAIL HOLD RIN 6.5k TRACK
CHOLD 18pF COMPARATOR
Figure 4. Equivalent Input Circuit
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Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
holding capacitor CHOLD through RIN. At the end of acquisition the T/H switch opens and CHOLD is connected to COM, retaining charge on CHOLD as a sample of the signal at CH0, and the difference between CH0 and COM is the converted signal. Once conversion is complete, the T/H returns immediately to its tracking mode. This procedure holds for the different combinations summarized in Table 2. The time available for the T/H to acquire an input signal (tACQ) is determined by the clock frequency, and is 1s at the maximum clock frequency of 2MHz. The acquisition time is also the minimum time needed for the signal to be acquired. It is calculated by: tACQ = 6(RS + RIN)18pF where RIN = 6.5k, RS = the source impedance of the input signal, and t ACQ is never less than 1s. Note that source impedances below 2.7k do not significantly affect the AC performance of the ADC at the maximum clock speed. If the input-source impedance is higher than 3k, the clock speed must be reduced accordingly. Pseudo-Differential Input The MAX1108/MAX1109 input configuration is pseudodifferential to the extent that only the signal at the sampled input (SI) is stored in the holding capacitor (CHOLD). The reference input (RI) must remain stable within 0.5LSB (0.1LSB for best results) in relation to GND during a conversion. Sampled input and reference input configuration is determined by bit6-bit4 (SEL2-SEL0) of the control byte (Table 2). If a varying signal is applied at the selected reference input, its amplitude and frequency need to be limited. The following equations determine the relationship between the maximum signal amplitude and its frequency to maintain 0.5LSB accuracy: Assuming a sinusoidal signal at the reference input vRI = VRIsin(2ft) the maximum voltage variation is determined by: max dvRI dt = 2f vRI 1 LSB t CONV = VREF
8
The input configuration selection also determines unipolar or bipolar conversion mode. The commonmode input range of CH0, CH1, and COM is 0 to +VDD. In unipolar mode, full scale is achieved when (SI - RI) = VREF; in bipolar mode, full scale is achieved when (SI - RI) = VREF / 2. In unipolar mode, SI must be higher than RI; in bipolar mode, SI can span above and below RI provided that it is within the common-mode range. Conversion Process The comparator negative input is connected to the autozero rail. Since the device requires only a single supply, the ZERO node at the input of the comparator equals VDD/2. The capacitive DAC restores node ZERO to have 0V difference at the comparator inputs within the limits of 8-bit resolution. This action is equivalent to transferring a charge of 18pF(VIN+ - VIN-) from CHOLD to the binary-weighted capacitive DAC which, in turn, forms a digital representation of the analog-input signal. Input Voltage Range Internal protection diodes that clamp the analog input to VDD and AGND allow the channel input pins (CH0, CH1, and COM) to swing from (AGND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions, the inputs must not exceed (VDD + 50mV) or be less than (GND - 50mV). If the analog input voltage on an "off" channel exceeds 50mV beyond the supplies, the current should be limited to 2mA to maintain conversion accuracy on the "on" channel. The MAX1108/MAX1109 input range is from 0 to VDD; unipolar or bipolar conversion is available. In unipolar mode, the output code is invalid (code zero) when a negative input voltage (or a negative differential input voltage) is applied. The reference input-voltage range at REF is from 1V to (VDD + 50mV.) Input Bandwidth The ADC's input tracking circuitry has a 1.5MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
MAX1108/MAX1109
2 t CONV a 60Hz signal at RI with an amplitude of 1.2V will generate a 0.5LSB of error. This is with a 35s conversion time (maximum tCONV in internal conversion mode) and a reference voltage of +4.096V. When a DC reference voltage is used at RI, connect a 0.1F capacitor to GND to minimize noise at the input.
Serial Interface
The MAX1108/MAX1109 have a 4-wire serial interface. The CS, DIN, and SCLK inputs are used to control the device, while the three-state DOUT pin is used to access the result of conversion.
______________________________________________________________________________________
11
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
The serial interface provides easy connection to microcontrollers with SPI, QSPI and MICROWIRE serial interfaces at clock rates up to 2MHz. For SPI and QSPI, set CPOL = CPHA = 0 in the SPI control registers of the microcontroller. Figure 5 shows the MAX1108/MAX1109 common serial-interface connections. Digital Inputs The logic levels of the MAX1108/MAX1109 digital input are set to accept voltage levels from both +3V and +5V systems, regardless of the supply voltages. Input data (control byte) is clocked in at the DIN pin on the rising edge of serial clock (SCLK). CS is the standard chipselect signal which enables communication with the device. SCLK is used to clock data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. Digital Output Output data is read on the rising edge of SCLK at DOUT, MSB first (D7). In unipolar input mode, the output is straight binary. For bipolar input mode, the output is twos-complement (see Transfer Function section). DOUT is active when CS is low and high impedance when CS is high. DOUT does not accept external voltages greater than VDD. In external-clock mode, data is clocked out at the maximum clock rate of 500kHz while conversion is in progress. In internal-clock mode, data can be clocked out at up to 2MHz clock rate.
Modes of Operation
The MAX1108/MAX1109 feature single-ended or pseudo-differential operation in unipolar or bipolar configuration. The device is programmed through the input control-byte at the DIN pin of the serial interface (Table 1). Table 2 shows the analog-input configuration and Table 3 shows the input-voltage ranges in unipolar and bipolar configuration.
How to Start a Conversion
A conversion is started by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1108/MAX1109's internal shift register. After CS falls, the first arriving logic "1" bit at DIN defines the MSB of the control byte. Until this first start bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. Using the Typical Operating Circuit (Figure 3), the simplest software interface requires two 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and one 8-bit transfer to clock out the 8-bit conversion result). Figure 6 shows a single-conversion timing diagram using external clock mode.
I/O SCK MISO MOSI
CS SCLK DOUT DIN
+3V
SS a) SPI CS SCK MISO MOSI CS
MAX1108 MAX1109
Clock Modes
The MAX1108/MAX1109 can use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the devices. Bit 3 of control-byte (I/ECLK) programs the clock mode. Figure 8 shows the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital conversion steps. In this mode the clock frequency must be between 50kHz and 500kHz. Single-conversion timing using an external clock begins with a falling edge on CS. When this occurs, DOUT leaves the high impedance state and goes low. The first "1" clocked into DIN by SCLK after CS is set low is considered as the start bit. The next seven clocks latch in the rest of the control byte. On the falling edge of the fourth clock, track mode is enabled, and on the falling edge of the sixth clock, acquisition is complete and conversion is
SCLK DOUT DIN
+3V
SS b) QSPI I/O SK SI SO CS
MAX1108 MAX1109
SCLK DOUT DIN
MAX1108 MAX1109
c) MICROWIRE
Figure 5. Common Serial-Interface Connections 12
______________________________________________________________________________________
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
Table 1. Control Byte Format
BIT 7 (MSB) START BIT 7 (MSB) 6 5 4 3 2 BIT 6 SEL2 NAME START SEL2 SEL1 SEL0 I/ECLK I/EREF BIT 5 SEL1 BIT 4 SEL0 BIT 3 I/ECLK BIT 2 I/EREF BIT 1 REFSHDN BIT 0 (LSB) SHDN
DESCRIPTION The first logic "1" bit after CS goes low defines the beginning of the control byte. Selects the mode of operation (Table 2). 1 = external clock, 0 = internal clock. The SAR can be driven by the internal oscillator, or with the SCLK signal. 1 = internal reference, 0 = external reference. Internal reference selects +2.048V (MAX1108) or +4.096V (MAX1109), or an external reference can be applied to the REF pin. 1 = operational (if I / EREF = 1), 0 = reference shutdown. When using an external reference, power consumption can be minimized by powering down the internal reference separately (I / EREF = 0). REFSHDN must be set to 0 when SHDN = 0. 1 = operational, 0 = power down. For a full power down set REFSHDN = SHDN = 0. (See PowerDown Mode section.)
1
REFSHDN
0 (LSB)
SHDN
Table 2. Conversion Configuration
SEL2 1 1 1 1 0 0 0 0 SEL1 1 1 0 0 1 1 0 0 SEL0 1 0 1 0 1 0 1 0 SAMPLED INPUT (SI) CH0 CH1 CH0 CH1 CH0 CH1 CH0 VDD / 2 REFERENCE INPUT (RI) COM COM GND GND COM COM CH1 GND CONVERSION MODE Unipolar Unipolar Unipolar Unipolar Bipolar Bipolar Bipolar Unipolar
Table 3. Full- and Zero-Scale Voltages
UNIPOLAR MODE Zero Scale RI* *RI = Reference Input (Table 2) ______________________________________________________________________________________ 13 Full Scale RI + VREF Negative Full Scale RI - VREF / 2 BIPOLAR MODE Zero Scale RI Positive Full Scale RI + VREF / 2
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
initiated. The MSB successive-approximation bit decision is made on the rising edge of the seventh SCLK. On the falling edge of the eighth SCLK, the MSB is clocked out on the DOUT pin; on each of the next seven SCLK falling edges, the remaining bits of conversion are clocked out. Zeros are clocked out on DOUT after the LSB has been clocked out, until CS is disabled. Then DOUT becomes high impedance and the part is ready for another conversion (Figure 6). The conversion must complete in 1ms, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the serial-clock frequency is less than 50kHz, or if serial-clock interruptions could cause the conversion interval to exceed 1ms. Internal Clock Internal clock mode frees the P from the burden of running the SAR conversion clock. This allows the conversion results to be read back at the processor's convenience, at any clock rate up to 2MHz. An internal register stores data when the conversion is in progress. On the falling edge of the fourth SCLK, track mode is enabled, and on the falling edge of the eighth SCLK, acquisition is complete and internal conversion is initiated. The internal 400kHz clock completes the conversion in 20s typically (35s max), at which time the MSB of the conversion is present at the DOUT pin. The falling edge of SCLK clocks the remaining data out of this register at any time after the conversion is complete (Figure 8).
CS
1
4
8 LSB
12
16
20
SCLK
MSB SEL2 SEL1 SEL0 I/ECLK I/EREF REF SHDN
SHDN
DIN
START
MSB
LSB D6 D5 D4 D3 D2 D1 D0
DOUT tACQ IDLE
D7
A/D STATE
tCONV
IDLE
Figure 6. Single Conversion Timing, External Clock Mode
CS *** tCSH SCLK tDS tDH DIN tDV DOUT *** *** tDO tTR tCSS tCL tCH *** tCSH
Figure 7. Detailed Serial-Interface Timing 14 ______________________________________________________________________________________
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX1108/MAX1109 and three-states DOUT, but it does not adversely affect an internal clock-mode conversion already in progress. In this mode, data can be shifted in and out of the MAX1108/MAX1109 at clock rates up to 2MHz, provided that the minimum acquisition time (tACQ) is kept above 1s.
Quick Look
To quickly evaluate the MAX1108/MAX1109's analog performance, use the circuit of Figure 9. The device requires a control byte to be written to DIN before each conversion. Tying CS to GND and DIN to VDD feeds in control bytes of FFH. In turn, this triggers single-ended, unipolar conversions on CH0 in relation to COM in external clock mode without powering down between conversions. Apply an external 50kHz to 500kHz clock
MAX1108/MAX1109
CS
SCLK
1
4
8
10
14
18
SEL2 SEL0 SEL1 I/EREF I/ECLK
DIN DOUT
REF SHDN SHDN
START D7 D6 D5 D4 D3 D2 D1 D0
A/D STATE
IDLE
tACQ
tCONV IDLE 35s MAX
Figure 8. Single Conversion Timing, Internal Clock Mode
VDD 0.1F 1F
VSUPPLY
OSCILLOSCOPE
DOUT* MSB LSB SCLK
MAX1108 MAX1109
ANALOG INPUT 0.01F CH0
GND CS SCLK
COM
DIN DOUT
VDD
500kHz OSCILLATOR
5s/div CH1 CH2
REF C1 1F
*CONVERSION RESULT = 10101010
Figure 9. Quick-Look Schematic ______________________________________________________________________________________ 15
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
to the SCLK pin; varying the analog input alters the result of conversion that is clocked out at the DOUT pin. A total of 10 clock cycles is required per conversion. In external clock mode, the first high bit clocked into DIN after the bit 5 (D5) of a conversion in progress is clocked onto the DOUT pin. OR In internal clock mode, the first high bit clocked into DIN after the bit 4 (D4) is clocked onto the DOUT pin. The MAX1108/MAX1109 can run at a maximum speed of 10 clocks per conversion. Figure 10 shows the serialinterface timing necessary to perform a conversion every 10 SCLK cycles in external clock mode. Many microcontrollers require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a microcontroller can drive the MAX1108/MAX1109. Figure 11 shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode.
Data Framing
The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. Acquisition starts on the falling edge of the fourth SCLK and lasts for two SCLKs in external clock mode or four SCLKs in internal clock mode. Conversion starts immediately after acquisition is completed. The start bit is defined as: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR
CS 1 SCLK DIN S CONTROL BYTE 0 S CONTROL BYTE 1 S CONTROL BYTE 2 S 8 10 1 10 1 10 1
CONVERSION RESULT 0 DOUT tACQ D7 D5 tCONV D0 tACQ D7
CONVERSION RESULT 1 D5 tCONV D0 tACQ D7 tCONV
A/D STATE
IDLE
Figure 10. Continuous Conversion, External Clock Mode, 10 Clocks/Conversion Timing
CS 1 SCLK DIN S CONTROL BYTE 0 CONVERSION RESULT 0 DOUT D7 D0 D7 S CONTROL BYTE 1 CONVERSION RESULT 1 D0 S 8 17 25
Figure 11. Continuous Conversion, External Clock Mode, 16 Clocks/Conversion Timing 16 ______________________________________________________________________________________
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
In external clock mode, if CS is toggled before the current conversion is complete, the current conversion is terminated, and the next high bit clocked into DIN is recognized as a new start bit. This can be useful in extending acquisition time by selecting conversion on the same channel with the second control byte (doubleclocking mode), effectively extending acquisition to 6 SCLKs. This technique is ideal if the analog input source has high impedance, or if it requires more than 1s to settle; it can also be used to allow the device and the reference to settle when using power downmodes (see Power-Down Modes section).
MAX1108/MAX1109
Table 4. Power-Down Modes of the MAX1108/MAX1109
BIT 2-BIT 0 OF CONTROL BYTE I/EREF REFSHDN 1 1 SHDN 1 Device Active/Internal Reference Active Device Active; Internal reference powered down after conversion, powered up at next start bit. Device Active/External Reference Mode Device and internal reference powered down after conversion, powered up at next start bit. Device powered down after each conversion, powered up at next start bit. External Reference Mode. Reserved. Do not use. OPERATING MODE
1
0
1
__________Applications Information
0 X 1
Battery Monitoring Mode
This mode of operation samples and converts the midsupply voltage, VDD / 2, which is internally generated. Set SEL2 = SEL1 = SEL0 = 0 in the control byte to select this configuration. This allows the user to monitor the condition of a battery providing VDD. The reference voltage must be larger than VDD / 2 for this mode of operation to work properly. From the result of conversion (CODE), V DD is determined as follows: VDD = CODE * VREF / 128.
1 0 0
0 1 X = Don't care
X 1
0 0
Power-On Configuration
When power is first applied, the MAX1108/MAX1109's reference is powered down and SHDN is not enabled. The device needs to be configured by setting CS low and writing the control byte. Conversion can be started within 20s if an external reference is used. When using the internal reference, allow 12ms for the reference to settle. This is done by first performing a configuration conversion to power up the reference and then performing a second conversion once the reference is settled. No conversions should be considered correct until the reference voltage (internal or external) has stabilized.
Power-Down Modes
To save power, place the converter into low-current power-down mode between conversions. Minimum power consumption is achieved by programming REFSHDN = 0 and SHDN = 0 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the conversion. If the control byte contains REFSHDN = 0, then the reference will turn off at the end of conversion. If SHDN = 0, then the chip will power-down at the end of conversion (in this mode I/EREF or REFSHDN should also be set to zero). Table 4 lists the power-down modes of the MAX1108/ MAX1109.
The first logical 1 clocked into DIN after CS falls powers up the MAX1108/MAX1109 (20s required for the device to power up). The reference is powered up only if internal reference was selected during the previous conversion. When the reference is powered up after being disabled, consider the settling time before using the result of conversion. Typically, 12ms are required for the reference to settle from a discharge state; less time may be considered if the external capacitor is not discharged completely when exiting shutdown. In all power-down modes, the interface remains active and conversion results may be read. Use the double clocking technique described in the Data Framing section to allow more time for the reference to settle before starting a conversion after short power-down.
Voltage Reference
The MAX1108/MAX1109 operate from a single supply and feature a software-controlled internal reference of +2.048V (MAX1108) and +4.096V (MAX1109). The device can operate with either the internal reference or an external reference applied at the REF pin. See the Power-Down Modes and Modes of Operation sections for detailed instructions on reference configuration. The reference voltage determines the full-scale range: in unipolar mode, the input range is from 0 to VREF; in bipolar mode, the input range spans RI VREF / 2 with RI = VREF / 2.
17
______________________________________________________________________________________
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
External Reference To use an external reference, set bit 2 (I/EREF) and bit 1 (REFSHDN) of control byte to 0 and connect the external reference (VREF between 1V and VDD) directly at the REF pin. The DC input impedance at REF is extremely high, consisting of leakage current only (typically 10nA). During a conversion, the reference must be able to deliver up to 20A average load current and have an output impedance of 1k or less at the conversion clock frequency. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 0.1F capacitor. MAX1109 has an internal reference of +4.096V. To use the device with supply voltages below 4.5V, external reference mode is required. With an external reference voltage of less than +2.048V (MAX1108) or +4.096V (MAX1109) at REF, the increase in the ratio of the RMS noise to the LSB value (FS / 256) results in performance degradation and decreased dynamic range. Internal Reference To use the internal reference, set bit 2 (I/EREF) and bit 1 (REFSHDN) of the control byte to 1 and bypass REF with a 1F capacitor to ground. The internal reference can be powered down after a conversion by setting bit 1 (REFSHDN) of the control byte to 0. When using the internal reference, use MAX1108 and MAX1109 with supply voltage below 4.5V and above 4.5V, respectively.
MAX1108/MAX1109
OUTPUT CODE 11111111 11111110 11111101
FULL-SCALE TRANSITION
FS = VREF + COM 1LSB = VREF 256 00000011 00000010 00000001 00000000 0 (COM) 1 2 3 INPUT VOLTAGE (LSB) FS FS - 1LSB
Figure 12a. Unipolar Transfer Function
OUTPUT CODE 01111111 01111110 +FS = VREF + COM 2 VREF COM = 2 -V -FS = REF + COM 2 VREF 1LSB = 256
00000010 00000001 00000000 11111111 11111110 11111101
Transfer Function
Table 4 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 12a depicts the nominal, unipolar I/O transfer function, and Figure 12b shows the bipolar I/O transfer function. The zero scale is determined by the input selection setting and is either COM, GND, or CH1. Code transitions occur at integer LSB values. Output coding is straight binary for unipolar operation and two's complement for bipolar operation. With a +2.048V reference, 1LSB = 8mV (VREF / 256).
10000001 10000000 -FS COM INPUT VOLTAGE (LSB) 1 +FS - 2 LSB
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or run digital lines underneath the ADC package. Figure 13 shows the recommended system-ground connections. A single-point analog ground (star-ground point) should be established at the A/D ground. Connect all analog grounds to the star ground. No digital-system ground should be connected to this point.
18 Figure 12b. Bipolar Transfer Function
The ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the comparator in the ADC. Bypass the supply to the star ground with 0.1F and 1F capacitors close to the V DD pin of the MAX1108/MAX1109. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10 resistor can be connected to form a lowpass filter.
______________________________________________________________________________________
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
Chip Information
SYSTEM POWER SUPPLIES GND
MAX1108/MAX1109
TRANSISTOR COUNT: 2373
+3V/+5V
1F
10
0.1F GND COM VDD DGND VDD
MAX1108 MAX1109
DIGITAL CIRCUITRY
Figure 13. Power-Supply Connections
______________________________________________________________________________________
19
Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs MAX1108/MAX1109
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 0.114 D2 0.116 0.120 E1 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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